Faster Adder Circuits for Inputs with Prescribed Arrival Times

We present an algorithm that computes a Boolean circuit for an AND-OR path (i.e., a formula of type t0∧(t1∨(t2∧(. . . tm−1) . . . ) or t0∨(t1∧(t2∨(. . . tm−1) . . . )) with given arrival times for the input signals. Our objective function is delay, a generalization of depth. The maximum delay of the circuit we compute is log2 W+log2 log2 m+log2 log2 log2 m+5, where dlog2 W e is a lower bound on the delay of any circuit depending on inputs t0, . . . , tm−1 with prescribed arrival times. Since the carry bit computation in adders reduces to evaluating AND-OR paths, up to a small additive constant, an adder with the same delay can be constructed. Our method yields the fastest circuits both for AND-OR paths and adders in terms of delay known so far.